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A Systolic Algorithm for the k-Nearest Neighbors Problem.

, , and . IEEE Trans. Computers, 41 (1): 103-108 (1992)

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An efficient graph representation for arithmetic circuitverification., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1443-1454 (2001)Equivalence checking of integer multipliers., and . ASP-DAC, page 169-174. ACM, (2001)Advanced techniques for RTL debugging., , , and . DAC, page 362-367. ACM, (2003)Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking., , , , , , , and . FMCAD, volume 1166 of Lecture Notes in Computer Science, page 19-33. Springer, (1996)Algorithms for compacting error traces., and . ASP-DAC, page 99-103. ACM, (2003)Verification of arithmetic circuits using binary moment diagrams., and . Int. J. Softw. Tools Technol. Transf., 3 (2): 137-155 (2001)Space- and Time-Efficient BDD Construction via Working Set Control., , , and . ASP-DAC, page 423-432. IEEE, (1998)PHDD: an efficient graph representation for floating point circuit verification., and . ICCAD, page 2-7. IEEE Computer Society / ACM, (1997)A Systolic Algorithm for the k-Nearest Neighbors Problem., , and . IEEE Trans. Computers, 41 (1): 103-108 (1992)Verification of Arithmetic Circuits with Binary Moment Diagrams., and . DAC, page 535-541. ACM Press, (1995)