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An automated design flow for 3D microarchitecture evaluation., , , , , and . ASP-DAC, page 384-389. IEEE, (2006)Timing-driven maze routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (2): 234-241 (2000)A fast algorithm for context-aware buffer insertion., , and . DAC, page 368-373. ACM, (2000)Timing driven maze routing., , and . ISPD, page 208-213. ACM, (1999)ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks., , , , , , , , , and 1 other author(s). ISCA, page 13-26. ACM, (2017)Instruction set extension with shadow registers for configurable processors., , , , , and . FPGA, page 99-106. ACM, (2005)Understanding the energy efficiency of SMT and CMP with multiclustering., , , and . ISLPED, page 48-53. ACM, (2005)Microarchitecture evaluation with floorplanning and interconnect pipelining., , , , , , , and . ASP-DAC, page 8-15. ACM Press, (2005)Microarchitecture evaluation with physical planning., , , and . DAC, page 32-35. ACM, (2003)Accelerating Sequential Applications on CMPs Using Core Spilling., , , , and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1094-1107 (2007)