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N-PVT Variation Detection Method.

T. Lee, T. Tsai, W. Lin, U. Chio, and C. Wang. IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 116-120 (2019)

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Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

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2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.C. Wang, Z. Hou, Y. Deng, U. Chio, and W. Wang. J. Circuits Syst. Comput., 29 (6): 2050088:1-2050088:17 (2020)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)A random shifting data weighted averaging algorithm for Nyquist-rate DAC.J. Yuan, L. Wu, U. Chio, Y. Wang, and Y. Wang. IEICE Electron. Express, 20 (20): 20230302 (2023)A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.H. Wei, U. Chio, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1192-1195. IEEE, (2008)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.G. Yin, U. Chio, H. Wei, S. Sin, S. U., R. Martins, and Z. Wang. ICECS, page 878-881. IEEE, (2010)A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.W. Wu, Y. Zhu, L. Ding, C. Chan, U. Chio, S. Sin, S. U., and R. Martins. ISCAS, page 2239-2242. IEEE, (2013)A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.Y. Zhu, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. IEEE J. Solid State Circuits, 45 (6): 1111-1121 (2010)A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. ISSCC, page 188-190. IEEE, (2011)A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.U. Chio, H. Wei, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1164-1167. IEEE, (2008)An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology.D. Muratore, A. Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, S. Sin, and R. Martins. ESSCIRC, page 421-424. IEEE, (2016)

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A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.

Please choose a person to relate this publication to

Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chio, U. Fat"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.

Please choose a person to relate this publication to

Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.