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A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.

, , and . IEEE Trans. Circuits Syst. Video Techn., 21 (2): 101-112 (2011)

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A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors., , and . DAC, page 670-675. ACM, (2009)Scalable Effort Hardware Design., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (9): 2004-2016 (2014)XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse., , , , , , , , , and 8 other author(s). CoRR, (2022)Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency., , , , and . DAC, page 555-560. ACM, (2010)Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator., , and . ISLPED, page 195-200. ACM, (2009)VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture., , , and . ICCD, page 260-265. IEEE Computer Society, (2010)Energy-efficient recognition and mining processor using scalable effort design., , , , and . CICC, page 1-4. IEEE, (2013)Low-power process-variation tolerant arithmetic units using input-based elastic clocking., , and . ISLPED, page 74-79. ACM, (2007)Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays., , , and . ASP-DAC, page 695-700. IEEE, (2011)IMPACT: imprecise adders for low-power approximate computing., , , , and . ISLPED, page 409-414. IEEE/ACM, (2011)