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Optimizing register binding in FPGAs using simulated annealing.

, and . ReConFig, IEEE Computer Society, (2005)

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Deadline-based connection setup in wavelength-routed WDM networks., , , and . Comput. Networks, 54 (11): 1792-1804 (2010)Optimizing register binding in FPGAs using simulated annealing., and . ReConFig, IEEE Computer Society, (2005)Register Binding for FPGAs with Embedded Memory., and . FCCM, page 167-175. IEEE Computer Society, (2004)Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course., , , , , , , and . IEEE Trans. Educ., 63 (4): 273-282 (2020)Efficient Resource Arbitration in Reconfigurable Computing Environments., and . DATE, page 560-566. IEEE Computer Society / ACM, (2000)An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications., , , and . DAC, page 616-622. ACM Press, (1999)A novel pseudorandom noise and band jammer generator using a composite sinusoidal function., , and . IEEE Trans. Signal Process., 58 (2): 535-543 (2010)Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers., and . DATE, page 650-657. IEEE Computer Society, (2001)Memory Synthesis for FPGA-Based Reconfigurable Computers., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 70-80. Springer, (2001)Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations., and . Journal of Circuits, Systems, and Computers, 24 (3): 1550039:1-1550039:19 (2015)