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Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

, , , , , , and . ITC, page 1041-1050. IEEE Computer Society, (2003)

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Verification and Validation of Complex Digital Systems: An Industrial Perspective., and . ISQED, page 11-12. IEEE Computer Society, (2001)Efficient Algorithmic Circuit Verification Using Indexed BDDs., , , , and . FTCS, page 266-275. IEEE Computer Society, (1994)Design rewiring based on diagnosis techniques., , and . ASP-DAC, page 479-484. ACM, (2001)Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification., , , and . IEEE Des. Test, 34 (5): 5-6 (2017)Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability., , , , and . ISQED, page 470-475. IEEE Computer Society, (2008)LEAF: A System Level Leakage-Aware Floorplanner for SoCs., , , , and . ASP-DAC, page 274-279. IEEE Computer Society, (2007)On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults., , and . ITC, page 398-406. IEEE Computer Society, (2002)Forward prediction based on wafer sort data - A case study., , , , and . ITC, page 1-10. IEEE Computer Society, (2011)Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained., , , and . ITC, page 1-10. IEEE Computer Society, (2008)Minimizing outlier delay test cost in the presence of systematic variability., , , and . ITC, page 1-10. IEEE Computer Society, (2009)