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Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO.

, , , and . SoCC, page 29-34. IEEE, (2016)

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Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO., , , and . SoCC, page 29-34. IEEE, (2016)An FPGA based Parallel Implementation for Point Cloud Neural Network., , , and . ASICON, page 1-4. IEEE, (2019)High-Speed Simultaneous Image Distortion Correction Transformations for a Multicamera Cylindrical Panorama Real-time Video System Using FPGA., , , , , and . IEEE Trans. Circuits Syst. Video Techn., 24 (6): 1061-1069 (2014)A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1430-1434 (2018)A FPGA real-time stereo vision system with luminance control and projected pattern., , , , and . ASICON, page 1-4. IEEE, (2013)Arbitrary shape multilayer interconnects EMC modelling and optimization., , , and . EMC Compo, page 87-91. IEEE, (2015)Modeling Simulation and Circuit Implementation of Millimeter Wave Phase-Locked Loop Based on Simulink., , and . ICICDT, page 1-4. IEEE, (2019)3D Anthropometric Algorithm from A Single Viewpoint RGB-D Camera., , and . ICACI, page 466-469. IEEE, (2020)Study of a FPGA real-time multi-cameras cylindrical panorama video system with low latency and high performance., , , , and . IVMSP, page 1-4. IEEE, (2013)Bridging Data Gaps in Healthcare: A Scoping Review of Transfer Learning in Biomedical Data Analysis., , , , , , , , , and 5 other author(s). CoRR, (2024)