Author of the publication

Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits.

, and . Journal of Circuits, Systems, and Computers, 18 (5): 899-908 (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

System Timing., and . The VLSI Handbook, CRC Press, (1999)Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)., , , and . Microprocess. Microsystems, 30 (7): 445-456 (2006)A single latch, high speed double-edge triggered flip-flop (DETFF)., and . ICECS, page 189-192. IEEE, (2001)Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (1): 12-27 (2004)Efficient CAD development for emerging technologies using Objective-C and Cocoa., , and . ICECS, page 369-372. IEEE, (2004)Advanced timing of level-sensitive sequential circuits., and . ICECS, page 603-606. IEEE, (2004)Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits., , , and . ISCAS (1), page 357-360. IEEE, (2002)LURU: global-scope FPGA technology mapping with content-addressable memories., , , and . ICECS, page 599-602. IEEE, (2004)Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew., and . Timing Issues in the Specification and Synthesis of Digital Systems, page 111-118. ACM, (2002)Delay insertion method in clock skew scheduling., and . ISPD, page 47-54. ACM, (2005)