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Design of Fault-Tolerant and Reliable Networks-on-Chip.

, , , , and . ISVLSI, page 545-550. IEEE Computer Society, (2015)

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Online Path-Based Test Method for Network-on-Chip., , , , and . ISCAS, page 1-5. IEEE, (2019)Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system., , , , and . Integr., (2019)Minimizing the system impact of router faults by means of reconfiguration and adaptive routing., , , , , and . Microprocess. Microsystems, (2017)Design of Fault-Tolerant and Reliable Networks-on-Chip., , , , and . ISVLSI, page 545-550. IEEE Computer Society, (2015)VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping., , , , , , and . MES@ISCA, page 18-25. ACM, (2016)Optimizing dynamic mapping techniques for on-line NoC test., , , , , , and . ASP-DAC, page 227-232. IEEE, (2018)A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip., , , , , , and . ASP-DAC, page 147-152. IEEE, (2018)Testing aware dynamic mapping for path-centric network-on-chip test., , , , , , and . Integr., (2019)Non-Blocking Testing for Network-on-Chip., , , , , , and . IEEE Trans. Computers, 65 (3): 679-692 (2016)A low latency fault tolerant transmission mechanism for Network-on-Chip., , , and . ISCAS, page 1-4. IEEE, (2017)