Author of the publication

Graphic rendering application profiling on a shared memory MPSOC architecture.

, , , and . DASIP, page 115-121. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture., , , , and . DATE, page 531-534. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Designing processors using MAsS, a modular and lightweight instruction-level exploration tool., , , and . DASIP, page 150-155. IEEE, (2011)When processors get old: Evaluation of BTI and HCI effects on performance and reliability., , , and . IOLTS, page 185-186. IEEE, (2013)A Compilation Framework for a Dynamically Reconfigurable Architecture., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1058-1067. Springer, (2002)Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study., , , and . DSD, page 390-397. IEEE Computer Society, (2009)Graphic rendering application profiling on a shared memory MPSOC architecture., , , and . DASIP, page 115-121. IEEE, (2011)Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration., , and . Technique et Science Informatiques, 24 (4): 395-422 (2005)Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture., , , and . ICASSP, page 4194. IEEE, (2002)A reconfigurable FIR/FFT unit for wireless telecommunication systems., , , and . FPL, page 645-648. IEEE, (2009)Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués., and . Technique et Science Informatiques, 29 (3): 345-378 (2010)