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FPGA implementation of a HW/SW platform for multimedia embedded systems.

, , , and . Des. Autom. Embed. Syst., 12 (4): 293-311 (2008)

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An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA., , , , , and . ICECS, page 814-817. IEEE, (2006)An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC., , , and . ATSIP, page 264-267. IEEE, (2016)HW/SW Codesign of the H.263 Video Coder., , , , , and . CCECE, page 783-787. IEEE, (2006)Analysis and Optimization of UB Video's H.264 Baseline Encoder Implementation on Texas Instruments' TMS320DM642 DSP., , , and . ICIP, page 3277-3280. IEEE, (2006)Optimization and Implementation on Fpga of the DCT/IDCT Algorithm., , , , , and . ICASSP (3), page 928-931. IEEE, (2006)Settling accuracy and noise performances in switched current grounded gate class AB memory cells., , and . ICECS, page 687-690. IEEE, (2003)Toward an optimal residual frame coding for DWT based video codec., , , , and . ICECS, page 876-879. IEEE, (2009)Real-time H.264/AVC baseline decoder implementation on TMS320C6416., , , , and . J. Real-Time Image Processing, 7 (4): 215-232 (2012)Fast coding unit selection and motion estimation algorithm based on early detection of zero block quantified transform coefficients for high-efficiency video coding standard., , , and . IET Image Processing, 10 (5): 371-380 (2016)Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard., , , , and . IEEE Trans. Consumer Electronics, 64 (4): 424-432 (2018)