Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.

T. Takemoto, M. Hayashi, C. Yoshimura, and M. Yamaoka. IEEE J. Solid State Circuits, 55 (1): 145-156 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takashi Seki

Makiko Takemoto

Takashi Iwata

Takashi Numaguchi

Takashi Tsuno

Other publications of authors with the same name

A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.T. Takemoto, M. Hayashi, C. Yoshimura, and M. Yamaoka. ISSCC, page 52-54. IEEE, (2019)A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects.T. Takemoto, H. Yamashita, T. Yazaki, N. Chujo, Y. Lee, and Y. Matsuoka. IEEE J. Solid State Circuits, 49 (10): 2259-2276 (2014)Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.Y. Sugie, Y. Yoshida, N. Mertig, T. Takemoto, H. Teramoto, A. Nakamura, I. Takigawa, S. ichi Minato, M. Yamaoka, and T. Komatsuzaki. CoRR, (2020)Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.Y. Sugie, Y. Yoshida, N. Mertig, T. Takemoto, H. Teramoto, A. Nakamura, I. Takigawa, S. ichi Minato, M. Yamaoka, and T. Komatsuzaki. Soft Comput., 25 (3): 1731-1749 (2021)7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.K. Yamamoto, K. Ando, N. Mertig, T. Takemoto, M. Yamaoka, H. Teramoto, A. Sakai, S. Takamaeda-Yamazaki, and M. Motomura. ISSCC, page 138-140. IEEE, (2020)FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search.T. Takemoto, N. Mertig, M. Hayashi, S. Susa-Tanaka, H. Teramoto, A. Nakamura, I. Takigawa, S. ichi Minato, T. Komatsuzaki, and M. Yamaoka. ReConFig, page 1-8. IEEE, (2018)A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver.T. Takemoto, Y. Matsuoka, Y. Sugiyama, H. Yonezawa, H. Yamashita, K. Adachi, T. Nakamura, E. Nomoto, K. Nakahara, H. Arimoto and 2 other author(s). OFC, page 1-3. IEEE, (2015)A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS.T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, T. Saito, and S. Nishimura. CICC, page 1-4. IEEE, (2010)10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator.K. Fukuda, H. Yamashita, F. Yuki, G. Ono, R. Nemoto, E. Suzuki, T. Takemoto, and T. Saito. ISSCC, page 186-187. IEEE, (2009)A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology.T. Takemoto, Y. Matsuoka, H. Yamashita, Y. Lee, H. Arimoto, M. Kokubo, and T. Ido. IEEE J. Solid State Circuits, 53 (5): 1518-1538 (2018)

BibSonomy

Disambiguation of "Takemoto, Takashi"