( en | de | ru )

 

Disambiguation of "Shu, Yun-Shiang"

Author of the publication

copydeleteadd this publication to your clipboard
A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection.

, , and . ISSCC, page 500-501. IEEE, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Lijin Shu

Shu Zhang

Bettina Yunis

Hyong-Sik Yun

Yong-Seon Yun

 

Other publications of authors with the same name

A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection., , and . ISSCC, page 500-501. IEEE, (2008)27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS., , and . ISSCC, page 458-459. IEEE, (2016)A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring., , , and . A-SSCC, page 1-4. IEEE, (2015)9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s., , , , , and . ISSCC, page 154-156. IEEE, (2020)Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters., , , and . CICC, page 1-8. IEEE, (2022)A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators.. VLSIC, page 26-27. IEEE, (2012)A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration., , , , and . CICC, page 157-160. IEEE, (2008)A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration., , , , and . IEEE J. Solid State Circuits, 44 (9): 2356-2365 (2009)F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits., , , , , and . ISSCC, page 517-519. IEEE, (2021)An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS., , , , and . ISSCC, page 334-336. IEEE, (2019)