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Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4466-4481 (2020)X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks., , , , and . ISPD, page 238-246. ACM, (2023)Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs., , , and . ICCAD, page 8. ACM, (2018)Security Closure of Physical Layouts ICCAD Special Session Paper., , , , , , , , and . ICCAD, page 1-9. IEEE, (2021)Concerted wire lifting: Enabling secure and cost-effective split manufacturing., , , and . ASP-DAC, page 251-258. IEEE, (2018)Rethinking split manufacturing: An information-theoretic approach with secure layout techniques., , , , , and . ICCAD, page 329-326. IEEE, (2017)Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging., , , and . ICCAD, page 41-48. IEEE, (2017)A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects., , , and . CoRR, (2019)Technical report: CoPHEE: Co-processor forPartially Homomorphic Encrypted Execution., , , , and . IACR Cryptol. ePrint Arch., (2021)A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL., , , , and . Cryptogr., 6 (2): 22 (2022)