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C++ simulator and FPGA emulator with shared register communication.

Y. Nakamura, K. Hosokawa, I. Kuroda, K. Yoshikawa, and T. Yoshimura. DAC, page 299-304. ACM, (2004)

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Insok Ko

Yousun Ko

Yousik Ko

Annette Ko

Ko Endo

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Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.T. Li, Y. Ma, K. Yoshikawa, O. Nomura, and T. Endoh. IEEE Trans. Ind. Informatics, 18 (5): 3055-3065 (2022)A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.Y. Nakamura, K. Hosokawa, I. Kuroda, K. Yoshikawa, and T. Yoshimura. DAC, page 299-304. ACM, (2004)Logic Synthesizer with Optimizations in Two Phases.K. Yoshikawa, and S. Muroga. The VLSI Handbook, CRC Press, (1999)Timing Optimization on Mapped Circuits.K. Yoshikawa, H. Ichiryu, H. Tanishita, S. Suzuki, N. Nomizu, and A. Kondoh. DAC, page 112-117. ACM, (1991)Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".T. Li, Y. Ma, K. Yoshikawa, and T. Endoh. IEEE Trans. Very Large Scale Integr. Syst., 31 (6): 906 (June 2023)Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.T. Li, Y. Ma, K. Yoshikawa, and T. Endoh. IEEE Trans. Very Large Scale Integr. Syst., 31 (7): 1078-1082 (2023)Domino Logic Synthesis System and its Applications.K. Yoshikawa, S. Inui, Y. Hagihara, Y. Nakamura, and T. Yoshimura. J. Circuits Syst. Comput., 15 (2): 277-287 (2006)Timing optimization by replacing flip-flops to latches.K. Yoshikawa, Y. Hagihara, K. Kanamaru, Y. Nakamura, S. Inui, and T. Yoshimura. ASP-DAC, page 186-191. IEEE Computer Society, (2004)An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.Y. Nakamura, K. Yoshikawa, and T. Yoshimura. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3351-3357 (2005)Budgeting-free hierarchical design method for large scale and high-performance LSIs.Y. Nakamura, M. Tagata, T. Okamoto, S. Tawada, and K. Yoshikawa. DAC, page 955-958. ACM, (2006)

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Disambiguation of "Yoshikawa, Ko"

Please choose a person to relate this publication to

Insok Ko

Yousun Ko

Yousik Ko

Annette Ko

Ko Endo

Other publications of authors with the same name

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Disambiguation of "Yoshikawa, Ko"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

Please choose a person to relate this publication to

Insok Ko

Yousun Ko

Yousik Ko

Annette Ko

Ko Endo

Other publications of authors with the same name

Disambiguation