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Disambiguation of "Moralis-Pegios, Miltiadis"

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High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture Invited.

, , , , , and . JOCN, 10 (7): B102-B116 (2018)

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Moralis Antonios

Miltiadis Mitsias

Wassilios Pegios

Antonios Moralis

Miltiadis Ioannu Iliopulos

 

Other publications of authors with the same name

High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture Invited., , , , , and . JOCN, 10 (7): B102-B116 (2018)Programmable tanh- and ReLU-like Optoelectronic Activation Functions for Neuromorphic Photonic Circuits., , , , , , , , and . OFC, page 1-3. IEEE, (2023)Chip-to-Chip Interconnect for 8-Socket Direct Connectivity Using 25Gb/s O-Band Integrated Transceiver and Routing Circuits., , , , , , , , , and 1 other author(s). ECOC, page 1-3. IEEE, (2018)A 1024-Port sub-µsee Latency Optical Packet Switch Using the Hipoλaos λ-Routed Modified Spanke Switch Architecture., , , , and . ECOC, page 1-3. IEEE, (2018)WDM equipped universal linear optics for programmable neuromorphic photonic processors., , , , , , , , and . Neuromorph. Comput. Eng., 2 (2): 24010 (2022)25GMAC/sec/axon photonic neural networks with 7GHz bandwidth optics through channel response-aware training., , , , , , , , and . ECOC, page 1-4. IEEE, (2021)Sub-μs Latency High-Port Optical Packet Switch Fabrics for Disaggregated Computing: The Hipoλaos OPS Architecture., , , , and . ICTON, page 1-4. IEEE, (2018)A Silicon Photonic Coherent Neuron with 10GMAC/sec processing line-rate., , , , , , , , , and . OFC, page 1-3. IEEE, (2021)On-Chip Universal Linear Optics using a 4x4 Silicon Photonic Coherent Crossbar., , , , , and . OFC, page 1-3. IEEE, (2023)DSP-free 52km-long dispersion uncompensated optical link employing a 40 Gb/s O-band silicon microring modulator assembled with a 1V-CMOS driver., , , , , , , , , and . OECC/PSC, page 1-3. IEEE, (2019)