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Disambiguation of "Singh, Adit D."

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Efficient SAT-based generation of hazard-activated TSOF tests.

, , , , and . VTS, page 1-6. IEEE Computer Society, (2017)

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Adit Ranadive

Somak Aditya

Dendy Adityawarman

Noviandi Meta Adityawarman

Sohan Singh

 

Other publications of authors with the same name

A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI., and . ICPP (1), page 261-265. Pennsylvania State University Press, (1989)Low-power domino circuits using NMOS pull-up on off-critical paths., , , and . ASP-DAC, page 533-538. ACM Press, (2005)Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (5): 818-830 (2018)A differential built-in current sensor design for high-speed IDDQ testing., and . IEEE J. Solid State Circuits, 32 (1): 122-125 (1997)Exploring the Mysteries of System-Level Test., , , , , , , , , and . ATS, page 1-6. IEEE, (2020)A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things., , , , and . VLSID, page 85-90. IEEE Computer Society, (2018)SEU tolerant robust memory cell design., , , and . IOLTS, page 13-18. IEEE Computer Society, (2012)Relating Yield Models to Burn-In Fall-Out in Time., and . ITC, page 77-84. IEEE Computer Society, (2003)Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design., , , , and . VLSI Design, page 606-612. IEEE Computer Society, (2006)Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations., , , , and . VLSI Design, page 711-716. IEEE Computer Society, (2007)