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An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors., , , , , , и . IEEE J. Solid State Circuits, 47 (11): 2627-2642 (2012)Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond., , , , , , , , , и 7 other автор(ы). CICC, стр. 1-8. IEEE, (2019)Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links., , , , , , , , , и 3 other автор(ы). CICC, стр. 605-608. IEEE, (2009)A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O., , , , , , , , , и . ISSCC, стр. 246-247. IEEE, (2010)A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking., , , , , , , , , и 10 other автор(ы). CICC, стр. 553-556. IEEE, (2005)A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking., , , , , , и . IEEE J. Solid State Circuits, 41 (8): 1894-1907 (2006)An Embedded All-Digital Circuit to Measure PLL Response., , , и . IEEE J. Solid State Circuits, 45 (8): 1492-1503 (2010)Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS., , , , , , , , , и 1 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits., , , , , , , , , и 1 other автор(ы). VLSID, стр. 98-103. IEEE, (2023)Nanoscale CMOS Implications on Analog/Mixed-Signal Design., , и . CICC, стр. 1-57. IEEE, (2019)