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Disambiguation of "sun Seo, Jae"

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High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS.

, , , , , and . ISSCC, page 182-183. IEEE, (2010)

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Sun-Aea Seo

Sun-Jae Lee

Sun-Jae Song

Jae-Sun Kim

Jae Sun Gross-Lee

 

Other publications of authors with the same name

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (7): 1354-1367 (2018)An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access., and . IEEE J. Solid State Circuits, 56 (3): 803-813 (2021)An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays., , , and . DATE, page 1019-1024. IEEE, (2020)A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC., , , , , , and . IEEE J. Solid State Circuits, 44 (10): 2755-2765 (2009)C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism., , , and . IEEE J. Solid State Circuits, 55 (7): 1888-1897 (2020)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3843-3853 (2019)Process Scalability of Pulse-Based Circuits for Analog Image Convolution., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2929-2938 (2018)In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , and . ISSCC, page 188-189. IEEE, (2010)NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking., , , , , , , , , and 61 other author(s). CoRR, (2023)A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware., , , , , , , and . J. Signal Process. Syst., 90 (5): 727-741 (2018)