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Disambiguation of "Min, Kyeong-Sik"

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Memristor-based cellular nanoscale networks: Theory, circuits, and applications.

, , , , , and . ISCAS, page 1134-1137. IEEE, (2015)

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Ky ng-sik Min

Georg Sikora

Arne Sikora

August Sikk

Matthias Sikora

 

Other publications of authors with the same name

Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing., , and . ASICON, page 1-4. IEEE, (2019)Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes., , and . J. Comput., 3 (3): 39-47 (2008)Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 430-435 (2006)Compact and efficient Maximum Power Point Tracking circuit for portable solar battery charger., , , and . IEICE Electron. Express, 8 (12): 930-937 (2011)Defect-Tolerant Crossbar Training of Memristor Ternary Neural Networks., , and . ICECS, page 486-489. IEEE, (2019)New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs., , , and . ISQED, page 459-464. IEEE Computer Society, (2009)Memristor models and circuits for controlling Process-VDD-Temperature variations., , and . ASICON, page 283-286. IEEE, (2011)Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes., , , and . IEICE Electron. Express, 8 (4): 232-238 (2011)A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs., , , , , , and . IEEE J. Solid State Circuits, 39 (11): 2087-2092 (2004)A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs., , , , , , , and . IEEE J. Solid State Circuits, 37 (2): 251-254 (2002)