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Concurrency characteristics in DSP programs., , and . ICASSP (2), page 433-436. IEEE Computer Society, (1994)Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification., , , , , and . DAC, page 964-969. ACM Press, (1999)An integrated system for rapid prototyping of high performance algorithm specific data paths., , , , , and . ASAP, page 134-148. IEEE, (1992)High level synthesis for reconfigurable datapath structures., , and . ICCAD, page 26-29. IEEE Computer Society / ACM, (1993)Design guidance in the power dimension., , and . ICASSP, page 2837-2840. IEEE Computer Society, (1995)Logic Optimization with Multi-Output Gates., , and . ICCD, page 416-420. IEEE Computer Society, (1993)A Methodology for Guided Behavioral-Level Optimization., , and . DAC, page 309-314. ACM Press, (1998)A partitioning scheme for optimizing interconnect power., , and . IEEE J. Solid State Circuits, 32 (3): 433-443 (1997)Instruction set mapping for performance optimization., , , , and . ICCAD, page 518-521. IEEE Computer Society / ACM, (1993)Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations., , and . ASAP, page 454-465. IEEE, (1993)