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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs., , , and . VLSI Signal Processing, 18 (1): 39-50 (1998)Critically Subsampled Filterbanks for SISO Reed-Solomon Decoding., , and . IEEE Trans. Signal Process., 54 (11): 4446-4460 (2006)Timing verification using statically sensitizable paths., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 10723-10784 (1990)Cellular automata based deterministic self-test strategies for programmable data paths., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (7): 940-949 (1994)DARSI: RC data reduction VLSI simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (4): 493-500 (1991)Acceleration of relaxation-based circuit simulation using a multiprocessor system., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 1063-1072 (1990)Combined hardware selection and pipelining in high-performance data-path design., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (4): 413-423 (1992)Efficient computation of symbol statistics from bit a priori information in turbo receivers., , , , and . IEEE Trans. Commun., 57 (7): 1889-1891 (2009)Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme., , and . IEEE Trans. Commun., 57 (4): 1031-1038 (2009)