Author of the publication

A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration.

, , and . ESSCIRC, page 269-272. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Session 26 overview: Nyquist-rate converters: Data converters subcommittee., and . ISSCC, page 456-457. IEEE, (2015)Redundancy in SAR ADCs., , and . ACM Great Lakes Symposium on VLSI, page 283-288. ACM, (2011)A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS., , and . IEEE J. Solid State Circuits, 50 (12): 2880-2890 (2015)Learning to Design Circuits., , , and . CoRR, (2018)16-channel oversampled analog-to-digital converter., , and . IEEE J. Solid State Circuits, 29 (9): 1077-1085 (September 1994)A mixed-signal array processor with early vision applications., , and . IEEE J. Solid State Circuits, 33 (3): 497-502 (1998)Radio frequency digital-to-analog converter., , and . IEEE J. Solid State Circuits, 39 (9): 1462-1467 (2004)A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC., and . IEEE J. Solid State Circuits, 31 (12): 1854-1861 (1996)Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators., , and . MWSCAS, page 562-565. IEEE, (2013)Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack., , and . CICC, page 1-2. IEEE, (2023)