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Disambiguation of "Masui, Shoichi"

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Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology.

, , , , , and . IEICE Trans. Electron., 94-C (3): 334-345 (2011)

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Shoichi Watanabe

 

Other publications of authors with the same name

Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm., , , and . IEICE Trans. Electron., 88-C (4): 576-581 (2005)A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 101-110 (2007)A ferroelectric memory-based secure dynamically programmable gate array., , , , , and . IEEE J. Solid State Circuits, 38 (5): 715-725 (2003)Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL., , and . IEICE Trans. Electron., 94-C (6): 1065-1068 (2011)A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology., , , , , , , , , and . ISSCC, page 1201-1210. IEEE, (2006)An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI., , , , , , , and . A-SSCC, page 265-268. IEEE, (2014)A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer., and . IEICE Electron. Express, 9 (4): 307-313 (2012)Hard to Track Objects with Irregular Motions and Similar Appearances? Make It Easier by Buffering the Matching Space., , , and . CoRR, (2022)Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology., , , , , and . IEICE Trans. Electron., 94-C (3): 334-345 (2011)Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (8): 1337-1346 (2012)