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Managing Leakage Energy in Cache Hierarchies.

, , , , , , и . J. Instruction-Level Parallelism, (2003)

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Fang-Yuh Lo

Fen-fang Tsai

Pei-Fang Tsai

Pei-Fang Frederika Tsai

Pei-Fang Frederika Tsai

 

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Leakage-Aware Interconnect for On-Chip Network, , , и . CoRR, (2007)Reducing leakage energy in FPGAs using region-constrained placement., , , , , и . FPGA, стр. 51-58. ACM, (2004)Implications of technology scaling on leakage reduction techniques., , , и . DAC, стр. 187-190. ACM, (2003)Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty., , , и . VLSI Design, стр. 374-379. IEEE Computer Society, (2005)Leakage-Aware Interconnect for On-Chip Network., , , и . DATE, стр. 230-231. IEEE Computer Society, (2005)Managing Leakage Energy in Cache Hierarchies., , , , , , и . J. Instruction-Level Parallelism, (2003)Design Space Exploration for 3-D Cache., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 16 (4): 444-455 (2008)Characterization and modeling of run-time techniques for leakage power reduction., , , и . IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1221-1233 (2004)Exploiting VLIW schedule slacks for dynamic and leakage energy reduction., , , , , и . MICRO, стр. 102-113. ACM/IEEE Computer Society, (2001)Evaluating Run-Time Techniques for Leakage Power Reduction., , , и . ASP-DAC/VLSI Design, стр. 31-38. IEEE Computer Society, (2002)