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New current-mode sense amplifiers for high density DRAM and PIM architectures.

, , , , and . ISCAS (4), page 938-941. IEEE, (2001)

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CMOS Pass-gate No-race Charge-recycling Logic (CPNCL)., and . ISCAS (1), page 226-229. IEEE, (1999)Low-voltage, high-speed circuit designs for gigabit DRAMs., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 32 (5): 642-648 (1997)2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test., , and . ACM Great Lakes Symposium on VLSI, page 93-96. ACM, (2001)Requirement-based design methods for adaptive communications links., , , , , and . DAC, page 93-98. ACM, (2004)The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management., , , and . J. Instr. Level Parallelism, (2001)No-Race Charge-Recycling Differential Logic (NCDL)., and . Great Lakes Symposium on VLSI, page 202-205. IEEE Computer Society, (1999)New high performance sub-1 V circuit technique with reduced standby current and robust data holding., and . ISCAS, page 65-68. IEEE, (2000)New current-mode sense amplifiers for high density DRAM and PIM architectures., , , , and . ISCAS (4), page 938-941. IEEE, (2001)Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques. University of Illinois Urbana-Champaign, USA, (2001)Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips., , , and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 152-159. Springer, (2000)