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Design and Implementation of a Handshake Join Architecture on FPGA., , , and . IEICE Trans. Inf. Syst., 95-D (12): 2919-2927 (2012)Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster., , , and . IEICE Trans. Inf. Syst., 94-D (12): 2319-2327 (2011)FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs., , , , , , and . FPL, page 473. IEEE, (2022)An Efficient Path Setup for a Photonic Network-on-Chip., , , , , and . ICNC, page 156-161. IEEE Computer Society, (2010)Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation., , , , , and . ICNC, page 228-234. IEEE Computer Society, (2011)Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA., , , and . MCSoC, page 84-91. IEEE Computer Society, (2012)OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip., , , , and . IWIA, page 3-10. IEEE, (2010)A Study of an Infrastructure for Research and Development of Many-Core Processors., , , and . PDCAT, page 414-419. IEEE Computer Society, (2009)Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption., and . SIGARCH Comput. Archit. News, 35 (5): 39-44 (2007)Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool., , , , and . HEART, page 8:1-8:6. ACM, (2017)