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Disambiguation of "Chae, Kwanyeob"

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On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing.

, , and . NANOARCH, page 128-133. IEEE Computer Society, (2013)

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Gyuwon Chae

Hong-Sik Chae

Yung-Bog Chae

Yi-Byung Chae

Jae-Ho Chae

 

Other publications of authors with the same name

A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (1): 74-83 (2014)Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface., , , , , and . ISOCC, page 140-141. IEEE, (2018)Low-power design under variation using error prevention and error tolerance (invited paper)., , and . LATW, page 1-6. IEEE Computer Society, (2012)22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique., , , , , , , , , and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)A dynamic timing control technique utilizing time borrowing and clock stretching., , , and . CICC, page 1-4. IEEE, (2010)On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing., , and . NANOARCH, page 128-133. IEEE Computer Society, (2013)All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation., and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 893-897 (2012)Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating., and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 173-177 (2014)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme., , , , , , , , , and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection., , , , , , , , , and 8 other author(s). ISSCC, page 406-407. IEEE, (2023)