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10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process.

, , , , and . ESSCIRC, page 245-248. IEEE, (2003)

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A Continuous Time ΔΣ ADC for Voice Coding with 92dB DR in 45nm CMOS., , , , , , and . ISSCC, page 502-503. IEEE, (2008)A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS., , , , and . DDECS, page 209-212. IEEE Computer Society, (2010)A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS, , , , and . CoRR, (2007)10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process., , , , and . ESSCIRC, page 245-248. IEEE, (2003)A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS., , , , and . DATE, page 223-226. IEEE Computer Society, (2004)A digitally controlled DC-DC converter for SoC in 28nm CMOS., , , , , , , , , and . ISSCC, page 384-385. IEEE, (2011)Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning, , and . The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04., 1, page 341--344. (July 2004)A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOS., , , , , and . ISSCC, page 832-841. IEEE, (2006)A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS., , and . CICC, page 437-440. IEEE, (2002)13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 218-219. IEEE, (2017)