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Allocating Lifetimes to Queues in Software Pipelined Architectures.

, , and . Euro-Par, volume 1300 of Lecture Notes in Computer Science, page 1066-1073. Springer, (1997)

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Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)A comparative study of modulo scheduling techniques., , and . ICS, page 97-106. ACM, (2002)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)Lightning Talks of EduHPC 2022., , , , , , , , , and 16 other author(s). EduHPC@SC, page 42-49. IEEE, (2022)Improved spill code generation for software pipelined loops., , , and . PLDI, page 134-144. ACM, (2000)Optimizing Program Locality Through CMEs and GAs., , , and . IEEE PACT, page 68-78. IEEE Computer Society, (2003)A fast and accurate framework to analyze and optimize cache memory behavior., , , and . ACM Trans. Program. Lang. Syst., 26 (2): 263-300 (2004)Using Sacks to Organize Registers in VLIW Machines., , , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 628-639. Springer, (1994)