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Disambiguation of "Wang, Yih"

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Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1199-1208 (2009)

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Yih-Fen Wang-Hua

Yiheyis Tasissa

Gabriel Yihune

Ming-Yih Lin

Dong-Yih Lin

 

Other publications of authors with the same name

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 172-179 (2008)Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (4): 1199-1208 (2009)Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 58 (1): 3-7 (2023)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 148-154 (2009)2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology., , , , , , , , , and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design., , , , , , and . IEEE Des. Test Comput., 28 (1): 22-31 (2011)15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture., , , , , , , , and . ISSCC, page 280-282. IEEE, (2024)An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications., , , , , , , , , and 10 other author(s). ISSCC, page 252-254. IEEE, (2021)13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology., , , , , , , , , and 2 other author(s). ISSCC, page 230-231. IEEE, (2014)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)