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Disambiguation of "Najm, Farid N."

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Managing verification error traces with bounded model debugging.

, , and . ASP-DAC, page 601-606. IEEE, (2010)

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Leo Najman

Oliver Najmann

Laurent Najman

Nour Addeen Najm

Juliane Najm

 

Other publications of authors with the same name

An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (11): 1372-1381 (1991)Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (2): 271-284 (2012)A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 574-591 (2007)Power Grid Fixing for Electromigration-induced Voltage Failures., , and . ICCAD, page 1-8. ACM, (2019)Verification of the Power and Ground Grids Under General and Hierarchical Constraints., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 729-742 (2016)Statistical Estimation of the Switching Activity in Digital Circuits., and . DAC, page 728-733. ACM Press, (1994)Guest Editorial., and . VLSI Design, (1998)Fast Vectorless RLC Grid Verification., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (3): 489-502 (2017)Energy-per-cycle estimation at RTL., and . ISLPED, page 121-126. ACM, (1999)Worst-case circuit delay taking into account power supply variations., , and . DAC, page 652-657. ACM, (2004)