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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.

H. Kimura, P. Aziz, T. Jing, A. Sinha, S. Kotagiri, R. Narayan, H. Gao, P. Jing, G. Hom, A. Liang, E. Zhang, A. Kadkol, R. Kothari, G. Chan, Y. Sun, B. Ge, J. Zeng, K. Ling, M. Wang, A. Malipatil, L. Li, C. Abel, and F. Zhong. IEEE J. Solid State Circuits, 49 (12): 3091-3103 (2014)

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Pervez Patel

Pervez Zamurrad Janjua

Farah Aziz

Faiz Ghanni Aziz

Majid Azizi

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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.H. Kimura, P. Aziz, T. Jing, A. Sinha, S. Kotagiri, R. Narayan, H. Gao, P. Jing, G. Hom, A. Liang and 13 other author(s). IEEE J. Solid State Circuits, 49 (12): 3091-3103 (2014)A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS.S. Quan, F. Zhong, W. Liu, P. Aziz, T. Jing, J. Dong, C. Desai, H. Gao, M. Garcia, G. Hom and 15 other author(s). ISSCC, page 348-350. IEEE, (2011)Analysis of a class of decimated clock/data recovery architectures for serial links.P. Aziz, and A. Malipatil. ISCAS, page 1175-1178. IEEE, (2013)Multi band sigma delta analog to digital conversion.P. Aziz, H. Sorensen, and J. der Spiegel. ICASSP (3), page 249-252. IEEE Computer Society, (1994)An overview of sigma-delta converters.P. Aziz, H. Sorensen, and J. der Spiegel. IEEE Signal Process. Mag., 13 (1): 61-84 (1996)Adaptation algorithms for a class of continuous time analog equalizers with application to serial links.P. Aziz, and A. Malipatil. ISCAS, page 1383-1386. IEEE, (2011)A class of downsampled floating tap DFE architectures with application to serial links.P. Aziz, H. Kimura, A. Malipatil, and S. Kotagiri. ISCAS, page 325-328. IEEE, (2012)A rate 16/17 punctured MTR block code.P. Aziz, N. Sayiner, and V. Annampedu. ICC, page 1643-1647. IEEE, (1999)Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems.P. Aziz, H. Sorensen, and J. der Spiegel. ISCAS, page 641-644. IEEE, (1995)Shift register multi-phase clock based downsampled floating tap DFE for serial links.P. Aziz, H. Kimura, A. Malipatil, S. Kotagiri, G. Chan, and H. Gao. ISCAS, page 2469-2472. IEEE, (2014)

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Disambiguation of "Aziz, Pervez M."

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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.

Please choose a person to relate this publication to

Pervez Patel

Pervez Zamurrad Janjua

Farah Aziz

Faiz Ghanni Aziz

Majid Azizi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Aziz, Pervez M."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.

Please choose a person to relate this publication to

Pervez Patel

Pervez Zamurrad Janjua

Farah Aziz

Faiz Ghanni Aziz

Majid Azizi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.