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Disambiguation of "Narayan, Ranjani"

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Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.

, , , , and . ICSAMOS, page 265-272. IEEE, (2010)

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Ranjani Dhakshinamoorthy

Rishikesh Narayan

Narayan Datar

Narayan Subramanian

Narayan Sircar

 

Other publications of authors with the same name

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat., , and . Circuits Syst. Signal Process., 34 (10): 3241-3290 (2015)Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design., , , , and . Parallel Process. Lett., 27 (3-4): 1750006:1-1750006:17 (2017)REDEFINE: Runtime reconfigurable polymorphic ASIC., , , , , , , , , and 1 other author(s). ACM Trans. Embed. Comput. Syst., 9 (2): 11:1-11:48 (2009)Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs., , , , , , , and . ICSAMOS, page 225-232. IEEE, (2014)Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures., , , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 204-215. Springer, (2009)A Framework for QoS Adaptive Grid Meta Scheduling., , , , and . DEXA Workshops, page 292-296. IEEE Computer Society, (2005)Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders., , , and . ASAP, page 287-292. IEEE Computer Society, (2008)Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array., , , , and . iNIS, page 7-12. IEEE, (2015)REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)., , , , , and . CASES, page 15:1-15:2. ACM, (2017)A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks., , , , , , , , and . VLSID, page 505-510. IEEE Computer Society, (2015)