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Disambiguation of "Wu, Sih-Sian"

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A Computational Efficient Architecture for Extremely Sparse Stereo Network.

, , , , and . ISCAS, page 1-5. IEEE, (2021)

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Benea Sih

Sian Brehler

Maria Sianidou

Robert Didier Ndzana Siani

Siân Leech

 

Other publications of authors with the same name

Joint Pruning & Quantization for Extremely Sparse Neural Networks., , , , and . CoRR, (2020)Hardware- and Memory-Efficient Architecture for Disparity Estimation of Large Label Counts., , and . IEEE Trans. Circuits Syst. Video Technol., 31 (9): 3679-3693 (2021)New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model., , , , and . DAC, page 258-261. ACM, (2010)CMWMF: Constant Memory Architecture of Weighted Mode/Median Filter for Extremely Large Label Depth Refinement., and . IEEE Trans. Circuits Syst. Video Technol., 31 (8): 2981-2993 (2021)A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os., , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Accurate and fast segment-based cost aggregation algorithm for stereo matching., , , and . MMSP, page 1-6. IEEE, (2017)Online Training Refinement Network and Architecture Design for Stereo Matching., , , and . ISCAS, page 1-5. IEEE, (2021)Video Stereo Matching with Temporally Consistent Belief Propagation., , , and . ICME, page 1-6. IEEE Computer Society, (2018)Memory efficient architecture for belief propagation based disparity estimation., , , and . ISCAS, page 2521-2524. IEEE, (2015)23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)