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SIR: A Secure Identifier-Based Inter-Domain Routing for Identifier/Locator Split Network.

Y. Liu, Z. Liu, B. Wang, и Q. Yang. IEICE Trans. Commun., 96-B (7): 1742-1752 (2013)

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Yang Yang

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On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator.M. Wen, N. Wu, C. Zhang, Q. Yang, J. Ren, Y. He, W. Wu, J. Chai, M. Guan, и C. Xun. IEEE Micro, 28 (4): 51-70 (2008)A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.N. Wu, Q. Yang, M. Wen, Y. He, C. Xun, и C. Zhang. Asia-Pacific Computer Systems Architecture Conference, том 4697 из Lecture Notes in Computer Science, стр. 256-267. Springer, (2007)Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.T. Xiao, Y. Qiao, J. Shen, Q. Yang, и M. Wen. ICA3PP (1), том 9528 из Lecture Notes in Computer Science, стр. 64-76. Springer, (2015)SAT: A Stream Architecture Template for Embedded Applications.Q. Yang, N. Wu, M. Wen, Y. He, H. Su, и C. Zhang. CIT, стр. 1711-1718. IEEE Computer Society, (2010)Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA.Z. Cao, H. Su, Q. Yang, M. Wen, и C. Zhang. INFOCOM Workshops, стр. 1057-1058. IEEE, (2019)Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA.Y. Qiao, J. Shen, D. Huang, Q. Yang, M. Wen, и C. Zhang. NPC, том 10578 из Lecture Notes in Computer Science, стр. 100-111. Springer, (2017)Enabling a Uniform OpenCL Device View for Heterogeneous Platforms.D. Huang, C. Xun, N. Wu, M. Wen, C. Zhang, X. Cai, и Q. Yang. IEICE Trans. Inf. Syst., 98-D (4): 812-823 (2015)Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications.H. Tan, R. Yan, L. Yang, L. Huang, L. Xiao, и Q. Yang. ICA3PP, том 13777 из Lecture Notes in Computer Science, стр. 642-659. Springer, (2022)Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression.Y. He, M. Guan, C. Zhang, T. Tian, и Q. Yang. HPCC-ICESS, стр. 25-32. IEEE Computer Society, (2012)Tiled Multi-Core Stream Architecture.N. Wu, Q. Yang, M. Wen, Y. He, J. Ren, M. Guan, и C. Zhang. Trans. High Perform. Embed. Archit. Compil., (2011)

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