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Cost-effective optimization of serial link system for Signal Integrity and Power Integrity.

, , and . ISQED, page 548-552. IEEE, (2011)

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Fast Analysis of Time Interval Error in Current-Mode Drivers., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 367-377 (2018)Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix., , and . IEEE Open J. Circuits Syst., (2020)Nonlinear modeling and analysis of buck converter using volterra series., , , and . ICECS, page 222-226. IEEE, (2017)I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)., , , and . VLSI-SoC, page 226-227. IEEE, (2019)Cost-effective optimization of serial link system for Signal Integrity and Power Integrity., , and . ISQED, page 548-552. IEEE, (2011)Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator., , , , , and . ISCAS, page 1-5. IEEE, (2019)Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms., , , , and . ISCAS, page 361-364. IEEE, (2012)Zero power 4.95Gbps HDMI transmitter., , , , and . ISCAS, page 1500-1503. IEEE, (2014)Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations., , , , , and . Sensors, 21 (18): 6074 (2021)A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell., , , and . ISCAS, page 1-5. IEEE, (2023)