Author of the publication

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).

, , , and . ISCAS (2), page 185-187. IEEE, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 900 MHz 1.2 V CMOS mixer with high linearity., , , and . APCCAS (1), page 1-4. IEEE, (2002)Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder., , , and . ISCAS, IEEE, (2006)Clock recovery circuit with adiabatic technology (quasi-static CMOS logic)., , , and . ISCAS (2), page 185-187. IEEE, (2003)Pipelines in Dynamic Dual-Rail Circuits., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 701-710. Springer, (2004)A New Control Circuit for Asynchronous Micropipelines., , , and . IEEE Trans. Computers, 50 (9): 992-997 (2001)An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 254-256 (2004)Pipelined Dataflow Architecture of a Small Processor., , , , , , and . PDPTA, page 1217-1223. CSREA Press, (1999)A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator., , , and . ESSCIRC, page 455-458. IEEE, (2005)0.8 V GPS band CMOS VCO with 29% Tuning Range., , , and . APCCAS, page 522-525. IEEE, (2006)Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System., , , and . APCCAS, page 195-198. IEEE, (2006)