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Hardware design of cryptographic accelerators.. University College Cork, Republic of Ireland, (2013)base-search.net (ftunivcollcork:oai:cora.ucc.ie:10468/1112).FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash., , , , , , and . IACR Cryptology ePrint Archive, (2009)An FPGA Technologies Area Examination of the SHA-3 Hash Candidate Implementations., and . IACR Cryptology ePrint Archive, (2009)A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem., , , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 355-361. Springer, (2009)Co-Z ECC scalar multiplications for hardware, software and hardware-software co-design on embedded systems., , , and . J. Cryptogr. Eng., 2 (4): 221-240 (2012)FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash., , , , , , and . DSD, page 783-790. IEEE Computer Society, (2009)Yet Another SHA-3 Round 3 FPGA Results Paper., and . IACR Cryptology ePrint Archive, (2012)FPGA Implementations of the Round Two SHA-3 Candidates., , , , , , and . FPL, page 400-407. IEEE Computer Society, (2010)A Hardware Wrapper for the SHA-3 Hash Algorithms., , , , , , and . IACR Cryptology ePrint Archive, (2010)