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Hardening the Software with Respect to Transient Errors: a Method and Experimental Results.

, , , , and . LATW, page 36-40. IEEE, (2000)

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A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks., , , , and . SBCCI, page 101-108. IEEE Computer Society, (2002)Hardening the Software with Respect to Transient Errors: a Method and Experimental Results., , , , and . LATW, page 36-40. IEEE, (2000)Dependability validation of a cryptoprocessor to SEU effects., , , and . LATW, page 1-6. IEEE, (2010)Operation in Space of Artificial Neural Networks Implemented by Means of a Dedicated Architecture based on a Transputer., , and . SBCCI, page 162-166. IEEE Computer Society, (1998)A soft-error resilient route computation unit for 3D Networks-on-Chips., , , , and . DATE, page 1357-1362. IEEE, (2018)NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip., , and . LATS, page 1-6. IEEE, (2019)Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied., , and . LATW, page 24-29. IEEE, (2001)Nanosatellite On-Board Computer including a Many-Core Processor., , , , , and . LATS, page 1-6. IEEE, (2021)Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation., , and . LATW, page 29-35. IEEE, (2000)Bit Flip Injection in Processor-Based Architectures: A Case Study., , , , , and . IOLTW, page 117-. IEEE Computer Society, (2002)