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Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.

, , , and . VLSID, page 563-564. IEEE Computer Society, (2016)

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A system-level solution for managing spatial temperature gradients in thinned 3D ICs., , , and . ISQED, page 88-95. IEEE, (2013)A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays., , and . IEEE Trans. Computers, 61 (7): 986-998 (2012)Symbolic implication in test generation., , , and . EURO-DAC, page 492-496. EEE Computer Society, (1991)Critical area driven dummy fill insertion to improve manufacturing yield., and . ISQED, page 334-341. IEEE, (2012)Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems., , and . IEEE Trans. Computers, 65 (3): 677-678 (2016)Preventing integrated circuit piracy via custom encoding of hardware instruction set., , and . ISQED, page 234-241. IEEE, (2016)Test Challenges in Nanometer Technologies., , , and . J. Electron. Test., 17 (3-4): 209-218 (2001)Pitfalls of hierarchical fault simulation.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 312-314 (2004)On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (3): 960-969 (2018)A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits., , and . ACM Great Lakes Symposium on VLSI, page 529-534. ACM, (2009)