From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies., , , и . CICC, стр. 1-4. IEEE, (2017)Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks., , , , , и . ESSCIRC, стр. 529-532. IEEE, (2022)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , и . VLSI Design, стр. 301-306. IEEE Computer Society, (2009)Ultra-low energy circuit building blocks for security technologies., , , и . DATE, стр. 391-394. IEEE, (2018)A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS., , , , , , , и . ESSCIRC, стр. 98-101. IEEE, (2018)μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS., , , , , , , , , и 1 other автор(ы). ESSCIRC, стр. 116-119. IEEE, (2015)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , и . ARITH, стр. 84-87. IEEE, (2019)A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures., , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2020)A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array., , , , , , , , , и 2 other автор(ы). VLSI Circuits, стр. 238-. IEEE, (2019)A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS., , , , , , , , и . CICC, стр. 1-4. IEEE, (2019)