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Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1356-1365 (2015)

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Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction., , , and . MMM (1), volume 8325 of Lecture Notes in Computer Science, page 541-552. Springer, (2014)VLSI architecture of HEVC intra prediction for 8K UHDTV applications., , , and . ICIP, page 1273-1277. IEEE, (2014)An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 52 (1): 113-126 (2017)A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder., , , , and . IEICE Trans. Electron., 94-C (4): 419-427 (2011)Reducing power consumption of HEVC codec with lossless reference frame recompression., , , and . ICIP, page 2120-2124. IEEE, (2014)A combined SAO and de-blocking filter architecture for HEVC video decoder., , , and . ICIP, page 1967-1971. IEEE, (2013)High Profile Intra Prediction Architecture for UHD H.264 Decoder., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec., , and . IEEE Trans. Multim., 16 (8): 2323-2332 (2014)Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC., , , , and . IEEE Trans. Multim., 19 (11): 2375-2390 (2017)Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks., , , and . DATE, page 1032-1037. IEEE, (2017)