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A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis.

, , , , and . SIGARCH Comput. Archit. News, 42 (4): 69-74 (2014)

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Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator., , , , , , , , , and 2 other author(s). IPSJ Trans. Syst. LSI Des. Methodol., (2010)Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs., , , and . Int. J. Netw. Comput., 12 (2): 387-405 (2022)Retrieving 3-d information with FPGA-based stream processing., , , , and . FPGA, page 261. ACM, (2008)Light-Weight Fine-Grain Dynamic Partial Reconfiguration on Xilinx FPGAs., , and . CISIS, volume 772 of Advances in Intelligent Systems and Computing, page 518-526. Springer, (2018)A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs., , and . CISIS, volume 993 of Advances in Intelligent Systems and Computing, page 453-461. Springer, (2019)Unsupervised Segmentation of Bibliographic Elements with Latent Permutations., , and . WISE Workshops, volume 6724 of Lecture Notes in Computer Science, page 254-267. Springer, (2010)Pipelined ADPCM Compression for HDR Synthesis on an FPGA., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 531-539 (2024)Documents as a Bag of Maximal Substrings - An Unsupervised Feature Extraction for Document Clustering., , and . ICEIS (1), page 5-13. SciTePress, (2011)A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis., , , , and . SIGARCH Comput. Archit. News, 42 (4): 69-74 (2014)Flexible Load-Dependent Soft-Start Method for Digital PID Control DC-DC Converter in 380Vdc System., , , , , and . IEICE Trans. Commun., 100-B (4): 518-528 (2017)