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Hybrid binary-unary hardware accelerator., и . ASP-DAC, стр. 210-215. ACM, (2019)3D FPGAs: placement, routing, and architecture evaluation (abstract only)., , и . FPGA, стр. 263. ACM, (2005)Timing-driven partitioning-based placement for island style FPGAs., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (3): 395-406 (2005)Placement and Routing in 3D Integrated Circuits., , , , , , и . IEEE Des. Test Comput., 22 (6): 520-531 (2005)Parallel Unary Computing Based on Function Derivatives., , , и . ACM Trans. Reconfigurable Technol. Syst., 14 (1): 4:1-4:25 (2020)Statistical Analysis and Design of HARP FPGAs., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2088-2102 (2006)Timing Minimization by Statistical Timing hMetis-based Partitioning., и . VLSI Design, стр. 58-63. IEEE Computer Society, (2003)Statistical Timing Driven Partitioning for VLSI Circuits., и . DATE, стр. 1109. IEEE Computer Society, (2002)Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing., , , , и . DATE, стр. 1757-1762. IEEE, (2019)Power and Area Efficient Sorting Networks Using Unary Processing., , , и . ICCD, стр. 125-128. IEEE Computer Society, (2017)