Author of the publication

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2148-2152 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A high-speed, programmable, CSD coefficient FIR filter., , and . IEEE Trans. Consumer Electronics, 48 (4): 834-837 (2002)A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (1): 14-24 (2020)A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment., , and . IEICE Electron. Express, 19 (11): 20220180 (2022)A wideband CMOS variable-gain low noise amplifier with novel attenuator., , , and . ASICON, page 1-4. IEEE, (2013)A high PSR SOI current-mode bandgap reference., , and . ASICON, page 1-4. IEEE, (2015)A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit., , and . ISCAS, page 448-451. IEEE, (2008)A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique., , , , and . CICC, page 53-56. IEEE, (2009)Author's Response., , , , and . IEEE J. Solid State Circuits, 43 (9): 2170 (2008)Comments on "Comments on Ä General Theory of Phase Noise in Electrical Oscillators""., , , , and . IEEE J. Solid State Circuits, 43 (9): 2170 (2008)A complementary fully differential dynamic comparator with insensitive common-mode mismatch., , , , and . IEICE Electron. Express, 19 (16): 20220274 (2022)