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An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems.

, and . Multim. Tools Appl., 76 (17): 17907-17922 (2017)

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Design and analysis of 3D IC-based low power stereo matching processors., , , and . ISLPED, page 15-20. IEEE, (2013)A census-based stereo matching algorithm with multiple sparse windows., , , and . ICUFN, page 240-245. IEEE, (2015)A Rectification Hardware Architecture for an Adaptive Multiple-Baseline Stereo Vision System., , , , and . FGIT-FGCN (1), volume 265 of Communications in Computer and Information Science, page 147-155. Springer, (2011)An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing., , , , , and . FGIT-FGCN (1), volume 265 of Communications in Computer and Information Science, page 136-146. Springer, (2011)A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000., , , , , and . FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 343-346. Springer, (2010)An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems., and . Multim. Tools Appl., 76 (17): 17907-17922 (2017)