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Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process.

, , , , , , and . IEICE Trans. Electron., 97-C (3): 188-193 (2014)

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Dividers., and . The VLSI Handbook, CRC Press, (1999)Recap of the 22nd Asia and South- Pacific Design Automation Conference.. IEEE Des. Test, 34 (3): 103-104 (2017)A fast addition algorithm for elliptic curve arithmetic in GF(2n) using projective coordinates., and . Inf. Process. Lett., 76 (3): 101-103 (2000)A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis., , and . IEEE Trans. Computers, 50 (5): 394-398 (2001)Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem., and . IEEE Trans. Computers, 41 (7): 887-891 (1992)High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree., , and . IEEE Trans. Computers, 34 (9): 789-796 (1985)On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic., and . IEEE Trans. Computers, 36 (11): 1310-1317 (1987)High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation., , and . IEICE Trans. Electron., 99-C (6): 703-709 (2016)Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process., , , , , , and . IEICE Trans. Electron., 97-C (3): 188-193 (2014)A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits., , , , , , , and . IEICE Trans. Electron., 97-C (3): 141-148 (2014)