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Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory.

, , , and . ISQED, page 577-582. IEEE, (2011)

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Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS., , , and . ISOCC, page 475-478. IEEE, (2012)Static energy minimization of 3D stacked L2 cache with selective cache compression., , , and . VLSI-SoC, page 228-233. IEEE, (2013)A low-energy video event data recorder using dual image/video codec., , , , , and . AVSS, page 277-282. IEEE Computer Society, (2014)Design and management of 3D-stacked NUCA cache for chip multiprocessors., , and . ACM Great Lakes Symposium on VLSI, page 91-96. ACM, (2011)Hybrid cache architecture replacing SRAM cache with future memory technology., , and . ISCAS, page 2481-2484. IEEE, (2012)Cost-effective TSV redundancy configuration., , , , and . VLSI-SoC, page 263-266. IEEE, (2012)Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory., , , and . ISQED, page 577-582. IEEE, (2011)Runtime 3-D stacked cache management for chip-multiprocessors., , , and . ISQED, page 68-72. IEEE, (2013)Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems., , and . VLSI-SoC, page 125-130. IEEE, (2010)Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors., , , and . ISQED, page 197-204. IEEE, (2014)