( en | de | ru )

 

Disambiguation of "Jou, Chewnpu"

Author of the publication

copydeleteadd this publication to your clipboard
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS.

, , , , , , , , , , , and . ISSCC, page 36-37. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nabil Al-Jou Jou

Shyi-Ming Jou

Yuan-jeh Jou

Axel Jourdant

Feodossi Jourtschenko

 

Other publications of authors with the same name

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology., , , , , , , , , and 3 other author(s). 3DIC, page TS6.3.1-TS6.3.4. IEEE, (2015)A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)Session 24 overview: 10GBase-T and optical front ends: Wireline subcommittee., and . ISSCC, page 408-409. IEEE, (2012)An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression., , , , , , , and . ISSCC, page 50-52. IEEE, (2012)D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link., , , , , , , and . CICC, page 1-4. IEEE, (2010)A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration., , , , , , , and . CICC, page 1-4. IEEE, (2012)A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX., , , , , , , , , and 1 other author(s). ESSCIRC, page 258-261. IEEE, (2010)A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing., , , , , and . ISSCC, page 414-415. IEEE, (2013)An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling., , , , , , , , , and . ISSCC, page 488-490. IEEE, (2011)